发明名称 ESD protection device with FET circuit
摘要 An FET is connected between ground and a pad to be protected from an ESD voltage, and when an ESD voltage appears at the pad the drain-channel junction breaks down and produces hole-electron pairs that turn on a parasitic bipolar transistor which clamps the voltage at the pad. A resistor connects the gate of the FET to ground. As the ESD voltage rises at the pad, the gate to drain capacitance charges in circuit with the resistor. The voltage across the gate oxide rises slowly enough that the FET is enabled to produce hole-electron pairs for turning on the bipolar transistor before the oxide voltage has reached a value that might damage the gate oxide.
申请公布号 US5563525(A) 申请公布日期 1996.10.08
申请号 US19950387083 申请日期 1995.02.13
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD 发明人 LEE, JIAN-HSING
分类号 H01L27/02;(IPC1-7):H02H9/04;H01L23/62 主分类号 H01L27/02
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