PURPOSE: An output buffer circuit is provided to improve an output noise characteristic influenced by a power line and increase operation speed of a device. CONSTITUTION: The output buffer circuit comprises: a first NOR gate(16) receiving sensed data of memory cell supplied from a first data line(A) and an output enable signal(OE) supplied from a first inverter(I11); a NOR gate(17) receiving sensed data of memory cell supplied from a second data line(B) and the output enable signal(OE) supplied from the first inverter(I11); an output data enable control circuit(11) for outputting a control signal according to the sensed data of memory cell supplied from the first and second data lines; a third NOR gate(15) for outputting a control voltage to a first node(K1) in accordance with an output of the data enable control circuit(11) and an external control signal(WE); a second inverter(I12) for supplying an inverted output of the first NOR gate(16) to a second node(K2); a third inverter(I13) for supplying an inverted output of the second NOR gate(17) to a third node(K3); an output voltage driving circuit(13) driven by output voltages of the first and second NOR gates supplied from the second and third nodes; a half Vcc control circuit(12) for maintaining an output potential of the output voltage driving circuit(13) at half Vcc according to the voltage of the first node(K1), coupled between the second and third nodes; and an output circuit(14) for providing an output data of the output voltage driving circuit(13) to an output terminal(Dout).
