Enhanced modularity in heterogeneous 3D stacks

摘要

A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan that includes receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to a layer in the 3D computer processing chip stack plan. The method also includes identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The method further includes determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment generates and integrates both the layer including the common structures and technologies and the host layer including the uncommon structures and technologies to form the 3D computer processing chip stack.

主权项

1. A method for generating and implementing a three-dimensional (3D) computer processing chip stack plan, the method comprising:
receiving system requirements from a plurality of clients; identifying common processing structures and technologies from the system requirements and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan, the common processing structures and technologies specifying properties of processing structures and technologies that are common to a defined quantity of the clients; identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan, the uncommon processing structures and technologies specifying properties of processing structures and technologies that have no commonality with a defined quantity of the clients; determining placement and wiring of the uncommon structures on the host layer, and storing placement information in the plan; and
transmitting the plan to manufacturing equipment, the manufacturing equipment generating both the at least one layer including the common structures and technologies and the host layer including the uncommon structures and technologies, and integrating the host layer and the at least one layer according to assignments and the placement information to form the 3D computer processing chip stack, the 3D computer processing chip stack comprising:
the host layer including cavities formed thereon for receiving chips pre-configured with heterogeneous properties relative to each other, the cavities formed to accommodate the heterogeneous properties of the chips,wherein the chips are joined to respective surfaces of the cavities thereby forming an element having a smooth surface with respect to the host layer and the chips.