| 摘要 |
<p>PURPOSE:To enable a clock with constant pulse width to be outputted by setting the OR of an input clock and a delay clock as an output clock, and setting delay quantity in which the pulse width is equal to a pulse width constant as the delay quantity. CONSTITUTION:A clock delay part 1 outputs the delay clock (b) by delaying the input clock (a) with a delay quantity signal (g), and an OR gate 2 generates the output clock (c) by computing the OR of the input clock (a) and the delay clock (b). A pulse width measuring circuit 3 measures the pulse width of the output clock (c), and outputs a pulse width signal (d), and a comparison part 4 outputs a comparison result (f) by comparing the pulse width signal (d) with the pulse width constant (e). A delay quantity holding part 5 accumulates the comparison result (f), and outputs the delay signal (g), and the delay quantity in which the pulse width of the output clock (c) can be kept constant shown in the pulse width constant (e) can be obtained at the clock delay part 1. Thereby, the clock with constant pulse width can be outputted as the output clock (c).</p> |
