Method and apparatus for transmitting digital data in massively parallel systems
摘要
<p>A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor. <MATH></p>
申请公布号
EP0687986(A2)
申请公布日期
1995.12.20
申请号
EP19950107081
申请日期
1995.05.10
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
GARMIRE, DERRICK LEROY;CAPOWSKI, ROBERT STANLEY;CASPER, DANIEL FRANCIS;DESNOYERS, CHRISTINE MARIE;FERRAIOLO, FRANK DAVID;HALMA, MARTEN JAN;STUCKE, ROBERT FREDERICK