Interleaving codewords over multiple flash planes

摘要

An apparatus having an interface to a plurality of memories and a circuit is disclosed. Each memory generally has a plurality of planes and is nonvolatile. The circuit is configured to (i) generate a plurality of codewords by encoding a plurality of data units, (ii) generate a plurality of slices by parsing the codewords, (iii) generate a plurality of pages by interleaving the slices and (iv) write the pages in parallel into respective ones of the planes.

主权项

1. An apparatus comprising:
a memory configured to store data; and a controller configured to process a plurality of input/output requests to read/write to/from the memory, generate a plurality of codewords by encoding a plurality of data units, assemble the plurality of codewords into a plurality of batches, generate a plurality of slices by parsing the plurality of batches, generate a plurality of data pages by interleaving the slices, and write the plurality of data pages in parallel into a plurality of planes in the memory, wherein each of the plurality of planes corresponds to one of the plurality of batches, each of the plurality of planes has a plurality of physical pages, and each of the plurality of data pages has a size that matches one of the plurality of physical pages.