Screening for Later Life Stuck Bits in Ferroelectric Memories

摘要

A reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays for stuck bits. The FRAM devices are subjected to a high temperature bake in wafer form. A “shmoo” of the reference voltage is performed, at an elevated temperature, for each device to identify a first reference voltage at which a first cell in the device fails a read of its low polarization capacitance data state, and a second reference voltage at which a selected number of cells in the device fail the read. The slope of the line between the first and second reference voltages, in the cumulative fail bit count versus reference voltage plane, is compared with a slope limit to determine whether any stuck bits are present in the device.

主权项

1. A method of testing an integrated circuit including memory cells of the ferroelectric one transistor—one capacitor (1T-1C) type, comprising the steps of:
baking the integrated circuit at a first elevated temperature for a selected duration; then, at a second elevated temperature lower than the first elevated temperature, reading each of a plurality of the memory cells programmed to a first data state corresponding to a lower polarization capacitance, at each of a plurality of reference voltages, to determine a first reference voltage at which a first one of the plurality of memory cells fails to return the first data state when read, and a second reference voltage at which a selected number of the plurality of memory cells fails to return the first data state when read; and comparing a slope of a line in the failed bit count versus reference voltage plane indicated by the first and second reference voltages with a slope limit to determine whether one or more of the plurality of memory cells constitute stuck bits.