| 摘要 |
PROBLEM TO BE SOLVED: To provide a highly integrated switching resistance RAM with which a readout time is shortened. SOLUTION: An NPN type bipolar transistor BT, in which an N well 11 is a collector layer, a P+ type Si layer 12A formed on a surface of the N wall 11 is a base layer, and an N+ type Si layer 15 formed on a surface of the P+ type Si layer 12A is an emitter layer, is formed. Further, a word line WL0 electrically connected to the N+ type Si layer 15 and bit lines BL1 to BL4 crossing the word line WL0 are formed. Furthermore, a plurality of switching layers 14 formed on the surface of the P+ type Si layer 12, electrically connected to corresponding bit lines, and switching between an ON state and an OFF state, and a potential-fixing line 19A for fixing the P+ type Si layer 12A at a predetermined potential are formed. COPYRIGHT: (C)2009,JPO&INPIT |
