| 摘要 |
<p>In an output buffer circuit for a memory including complementarily-connected P-channel and Nchannel MOS transistors, a voltage is induced across the lead inductance whenever the load capacitance is charged or discharged through the lead inductance during the switching operation of the buffer circuit. This induced voltage changes the ground level or the supply voltage level, and results in a problem such that data signals read from the memory are distorted. To overcome this problem, one of the two MOS transistors through which an electric charge is charged or discharged is divided into two MOS transistors of a small size, and the data signal is applied to one of the divided MOS transistor directly and to the other thereof through a delay element so that the peak of the induced voltage is lowered without increasing the access time of the memory.</p> |
