| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumption selectively outputting the output of a demodulating means or that of a demodulated data error rate improving means. SOLUTION: A DC voltage level is compared with a reference voltage by a comparator 10 and a delay detection system control signal 101 is outputted. The number of error packets is counted in respect to the number of sampling packets, an error rate is calculated, the calculated value is compared with a set value by a comparator 13, and a data error rate degradation detecting signal 105 is generated. The data error rate degradation detecting signal 105, delay detection system control signal 101 and frame synchronizing detecting signal 104 are synthesized by an OR circuit and a synthetic delay detection system control signal 103 is generated. In response to the synthetic delay detection system control signal 103, a switching control part 614 selects either of 1T and 2T delay detection data 615 and 616 and applies the selected data as MSK demodulation data 102 to a data demodulating part 7. At the same time, the synthetic delay detection system control signal 103 controls the supply/stop switching of operating clock of a 2T delay detection decoder circuit 61 as well. |
