发明名称 Caching bypass
摘要 In general, in one aspect, the disclosure describes a method that includes providing a memory access instruction of a processing element's instruction set including multiple parameters. The parameters include at least one address and a token specifying whether the instruction should cause data retrieved from memory in response to the memory access instruction to be unavailable to a subsequent memory access instruction via a cache
申请公布号 US7302528(B2) 申请公布日期 2007.11.27
申请号 US20040993579 申请日期 2004.11.19
申请人 INTEL CORPORATION 发明人 CABOT MASON B.;HADY FRANK T.;ROSENBLUTH MARK B.;TENNENHOUSE DAVID L.
分类号 G06F12/00 主分类号 G06F12/00
代理机构 代理人
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