| 摘要 |
<p>PURPOSE: To provide a signal detection circuit for receiving a digital signal that generates a synchronizing signal even when more or less errors are in existence. CONSTITUTION: An even number frame synchronizing signal detection section 11 in a synchronizing signal detection circuit for receiving a digital signal is provided with a shift register SR2 shifting an input signal, a gate group consisting of a plurality of gates EXOR1-EXOR64 connected to parallel output terminals and applying exclusive OR to output data and fixed data corresponding to the output data, a resistor group consisting of a plurality of resistors R connected to output terminals of the gate EXOR to sum output voltages, and a comparator COMP 1 that compares the sum output voltage with a reference voltage to provide an output, and an odd number frame synchronizing signal detection section 14 is configured similarly to the even number frame synchronizing signal detection section 11. The output voltage from the even/odd number frame synchronizing signal detection sections 11, 14 is compared with a reference voltage and synchronization is recognized independently of an error bit number. The detected odd and even frame synchronizing signals are ORed and a complete frame synchronizing signal is outputted.</p> |
