发明名称 |
Programmable Address-Based Write-Through Cache Control |
摘要 |
This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write- back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.
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申请公布号 |
US2012198164(A1) |
申请公布日期 |
2012.08.02 |
申请号 |
US201113247234 |
申请日期 |
2011.09.28 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
DAMODARAN RAGURAM;CHACHAD ABHIJEET ASHOK;BHORIA NAVEEN |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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