| 摘要 |
<p>Chip size and cost can be prevented from increasing. Capacitance and resistance depending on the layout of wiring formed for a plurality of wiring layers (S11-S16) are extracted as a capacitance/resistance file (S17), a best-worst capacitance/resistance file defining capacitance and resistance while taking account for variations in wiring for every wiring layer is created (S18) with reference to a best-worst coefficient file storing coefficients of best and worst conditions of variations in capacitance and resistance for every one of a plurality of wiring layers, and timing verification of wiring is performed (S19) based on the best-worst capacitance/resistance file.</p> |
