| 摘要 |
PURPOSE:To derive exactly a faulty address without halting a data transfer by storing all transfer request signals generated before a fault caused by the transfer request signal is detected from the transfer request signal, and generating the faulty address by counting back the transfer address signal at the time point when the fault is detected. CONSTITUTION:An issue request storage part 13 stores successively WRQ issued by a request issuing part 6, and supplies its storage request to a transfer request number operating part 14. The transfer reqeust number arithmetic part 14 supplies a request number calculating value (RQC) which becomes ''0'', ''1'' and ''2'' when RQD1-2 is ''00'', when it is ''01'' or ''10'', and when it is ''11'', respectively, to an address airthmetic part 15. The address arithmetic part 15 executes an operation for subtracting ''1'', ''2'', and ''2'' at the time of RQC=0, RQC=1 and RQC=2, respectively, with regard to WA3-5 issued by an address issuing part 7, and outputs an arithmetic address (CLA3-5) which is before a prescribed time of WA3-5. Basing on it, a faulty address in case when a fault is generated is generated. |
