| 摘要 |
An error checking apparatus includes first and second switching circuits arranged at input and output ports of a data processing circuit for processing data constituted by a plurality of parallel bits to be transferred through a plurality of transmission lines. The first and second switching circuits are switched so as to bit-shift the input/output connections in a normal mode and a test mode. An error detection control circuit is arranged to decide an error position and a cause of an error in accordance with contents of data obtained at the circuit output port before and after switching.
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