发明名称 CLOCK CONTROL SYSTEM
摘要 PURPOSE:To process trouble of an information processing system without a hitch by performing stop control over a clock in consideration of the connection position relation of an arithmetic process which is troubles among arithmetic processors when the processor is troubled. CONSTITUTION:A trouble factor signal generated by the arithmetic processor 31 is passed through a signal line L8, an OR gate 510, an AND gate 521, a signal line L55, an OR gate 514, and a signal line L12 to hold the output of an AND gate 611 at logical level '0'. Namely, the clock (signal line L16) of the arithmetic processor 31 stops. Therefore, only the arithmetic processor 31 is disconnected logically from the system. Further, if trouble occurs to an arithmetic processor 30, the outputs of AND gates 610 and 611 are held at the logical level '0'. Thus, the clocks of the arithmetic processors 30 and 31 are stopped and the processors are both disconnected logically from the system. In the two cases, arithmetic processors 40 and 41 are not affected at all.
申请公布号 JPH02100723(A) 申请公布日期 1990.04.12
申请号 JP19880252901 申请日期 1988.10.08
申请人 NEC CORP;KOUFU NIPPON DENKI KK 发明人 IWATA ATSUSHI;KASAI HIROYUKI
分类号 G06F15/16;G06F1/04;G06F1/10;G06F11/00;G06F11/07;G06F11/20;G06F15/177;G06F15/80 主分类号 G06F15/16
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