发明名称 MANUFACTURE OF MULTILAYER INTERCONNECTION CONDUCTOR PATTERN
摘要 PURPOSE: To provide a process of decreasing defects between the levels of a semiconductor chip, which is formed with via open parts using an RIE process. CONSTITUTION: Melallized levels 15 are covered with such a comparatively thick non-conformal oxide layer 24 as a quartz layer (SiO2 layer) formed by a sputtering method. Then, this layer 24 is covered with a blanket 20 consisting of such a comparatively thin oxide layer, which can stand an RIE, as an aluminium oxide layer (Al2 O3 layer) or a yttrium oxide layer (Y2 O3 layer). A mask having exposed via open parts is formed on the surface of this aluminium oxide layer 20 by a prior art technique and the aluminium oxide layer 20 in these opening regions is removed. The Al2 O3 layer 20 is etched using a wet etching method using BCL3 gas, for example, and O2 gas or H3 PO4 gas. Then, vias 22 are formed using an RIE process.
申请公布号 JPH0685074(A) 申请公布日期 1994.03.25
申请号 JP19930017956 申请日期 1993.01.08
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 DOU BIN NGUYAN;HAZARA ESU RASOORU
分类号 H01L23/52;H01L21/3205;H01L21/3213;H01L21/768;(IPC1-7):H01L21/90;H01L21/320 主分类号 H01L23/52
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