发明名称 |
Stacked memory device and system |
摘要 |
A stack memory device may include a core chip and a base chip. The core chip may include a data receiver, a strobe signal generation unit, and a test register. The data receiver may be configured for receiving data outputted from the core chip through a first normal port. The strobe signal generation unit may be configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode. The test register may store data outputted from the data receiver in response to the data strobe signal. |
申请公布号 |
US9396777(B1) |
申请公布日期 |
2016.07.19 |
申请号 |
US201514724027 |
申请日期 |
2015.05.28 |
申请人 |
SK hynix Inc. |
发明人 |
Lee Dong Uk |
分类号 |
G11C7/00;G11C7/22;G11C8/06;G11C8/18;G11C29/00;G11C5/02 |
主分类号 |
G11C7/00 |
代理机构 |
William Park & Associates Ltd. |
代理人 |
William Park & Associates Ltd. |
主权项 |
1. A stacked memory device, comprising:
a core chip and a base chip, wherein the base chip comprises: a data receiver configured to receive data outputted from the core chip through a first normal port; a strobe signal generation unit configured to generate a data strobe signal based on one of a normal strobe signal and a test strobe signal depending on an operation mode, wherein the test strobe signal is generated based on a signal received through a first test port; and a test register configured to store data outputted from the data receiver in response to the data strobe signal. |
地址 |
Icheon-si, Gyeonggi-do KR |