Ultra low power dual quantizer architecture for oversampling delta-sigma modulator

摘要

Power consumption of analog-to-digital converters (ADCs) is one important requirement for automotive and consumer devices. One flavor of an ADC is a dual quantizer architecture for oversampling delta-sigma modulators. The dual quantizer delta-sigma modulator has a first quantizer for digitizing the output of the loop filter and a second quantizer for digitizing the input of the quantizer. However, the quantization noise of the second quantizer is a highly correlated signal and significantly degrades the spectrum of the delta-sigma modulator. To address this issue, an improvement to the dual quantizer architecture is made to cancel the quantization noise of the second quantizer that is digitizing the input. Furthermore, the improvement allows the second quantizer to run at a much slower sampling rate than the first quantizer. Advantageously, the improvement provides reduction in power consumption and the overall area of modulator.

主权项

1. A delta-sigma modulator having a dual quantizer architecture for processing an analog input signal and generating a digital output signal representing the analog input signal at a digital output, the delta-sigma modulator comprising:
a loop filter for processing an error between the analog input signal to the delta-sigma modulator and a feedback signal from a feedback digital-to-analog converter (DAC); a first analog-to-digital converter (ADC) for digitizing an output of the loop filter of the delta-sigma modulator at a first sampling rate; and a second ADC for digitizing the analog input signal to the delta-sigma modulator at a second sampling rate different from the first sampling rate; wherein a quantization noise of the second ADC is cancelled at the digital output of the delta-sigma modulator.