Cache optimization for programming loops

摘要

A cache memory architecture 50, which may be, for example, a set associative cache memory, has a cache controller (52) with an internal register for storing the address of the active line currently latched in the output buffer of the high speed cache data array (56) which stores the cached data values from the main memory. If a memory access request specifies an address which would be contained in the active line, the cache look-up mechanisms are disabled and the data is taken from the output buffer. The efficiency of the cache can be increased by linking a program to memory such that the number of cache lines used by one or more program loops are minimized.