| 摘要 |
PURPOSE: A method for manufacturing a hybrid semiconductor device is provided to minimize damage to a peripheral circuit portion in a subsequent etching process for an interlayer dielectric, by forming a dummy pattern functioning as a guide ring on an interface between the peripheral circuit portion and a logic circuit portion. CONSTITUTION: A contact pad(49) is formed in a cell portion on a semiconductor substrate(41) having an isolation layer(43) and a word line(45). A wet-etch stop layer(51) is formed on the entire surface. The first interlayer dielectric(55), a bit line(57) and the second interlayer dielectric(59) are formed on the entire surface. A capacitor contact plug(61) is connected to the contact pad on the semiconductor substrate and a capacitor contact plug is formed on the wet-etch stop layer, wherein the capacitor contact plug formed on the wet-etch stop layer is located on an interface between a peripheral circuit portion and a logic circuit portion and used as a guard ring. A capacitor is formed only on the contact plug connected to the contact pad. After the first and second interlayer dielectrics in the logic circuit portion are etched and the wet-etch stop layer is dry-etched in a subsequent process, a silicide layer is formed in the logic circuit portion.
|
