| 摘要 |
<p>A non volatile memory device and its manufacturing method are provided to implement high integration by using one unit having two cells, thereby reducing a chip size less than a general EEPROM. An isolation layer(102) having an active area(110) is formed on a semiconductor substrate. Memory cell units arranged with matrix type are formed on the semiconductor substrate. The each memory cell units comprise a common source region(112), a selective gate(123) filling the common source region, a first memory gate(137a) provided on the active area adjacent to one side of the selective gate, a second memory gate(137b) provided on the active area adjacent to the other side of the selective gate, and a first and second drain regions(114,115) on the active area.</p> |
