| 摘要 |
PURPOSE:To attain an effective data transfer by performing the read or the write of a data only when it is effective. CONSTITUTION:At a most significant bit comparison circuit 32(n), the output of an AND gate 27 goes to a '1' level, and the output of an AND gate 28 to '0' level, and the outputs of OR gates 29 and 31 to '1' levels. In such a state, it is CMPnot equal to PD, and CMP<PD, and if it is necessary to read a port data by a CPU under such a condition, a control logic 35 sets a flag for the CPU. And the CPU, responding to the flag, outputs a read control signal RD by a software, or an interruption process, and makes operate an output gate circuit 24, then performing the read of the port data through an internal bus. On the other hand, when it is not necessary to read the port data by the CPU under the above condition, the control logic 35 sets no flags. Therefore, in this case, the CPU does not perform the wasteful read of the port data.
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