发明名称 MANUFACTURE OF IC PACKAGE
摘要 <p>PROBLEM TO BE SOLVED: To avoid connection defects between a build-up multilayer board to an IC chip. SOLUTION: An insulation layer 15 of the same depth as that of an IC chip 11 is formed on a core 13, the IC chip is fitted in a cavity 16 of the insulation layer 15 with its surface up at pads 12, and adhered to the core 13. A photosensitive resin layer 18 is formed on the same plane, formed by the surface of the IC chip 11 at the pads 12 and top surface of the insulation layer 15, and photoetched to form vias, via-conductors 20 and inner layer wiring pattern 21 are formed by plating from above them. Forming of the photosensitive resin layer 18, forming of the vias, and forming of the via-conductors 20 and inner layer wiring pattern 21 are repeated to form a build-up multilayer board 17 on the IC chip 11. A solder paste is printed on the top end portions of the via-conductors 20 of the topmost layer and molten by the reflow to form solder bumps 22.</p>
申请公布号 JPH11233678(A) 申请公布日期 1999.08.27
申请号 JP19980033130 申请日期 1998.02.16
申请人 SUMITOMO METAL ELECTRONICS DEVICES INC 发明人 AKAHO KAZUNORI
分类号 H05K3/46;H01L23/12;(IPC1-7):H01L23/12 主分类号 H05K3/46
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