| 摘要 |
An interface circuit includes a variable delay circuit and a delay adjustment circuit to automatically detect a data valid window of a DQ signal and adjust an optimum delay amount of a DQS signal, and a fixed delay circuit to delay the DQ signal by a delay amount t<SUB>FIXDLY </SUB>satisfying t<SUB>FIXDLY</SUB>>t<SUB>MINDLY</SUB>+t<SUB>SKEW</SUB>-t<SUB>SETUP </SUB>where a minimum delay amount in the variable delay circuit is t<SUB>MINDLY</SUB>, a skew between the DQ signal and the DQS signal is t<SUB>SKEW</SUB>, and a setup time of the DQ signal is t<SUB>SETUP</SUB>.
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