发明名称 Devices and operation methods for reducing second bit effect in memory device
摘要 A method for operating a semiconductor memory device having first and second bit lines, a gate electrode, an insulative layer, and a substrate includes applying first, second, and third biases to the first bit line, the second bit line, and the gate electrode, respectively, to induce carriers from the gate electrode to the insulative layer, where the carriers have the same type of conductivity as majority carriers in the substrate to thereby reduce a threshold voltage of the semiconductor memory device.
申请公布号 US7483299(B2) 申请公布日期 2009.01.27
申请号 US20060496441 申请日期 2006.08.01
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 HSU TZU-HSUAN;WU CHAO-I;LAI ERH-KUN
分类号 G11C11/03 主分类号 G11C11/03
代理机构 代理人
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