| 摘要 |
<p>The present invention relates generally to the field phase detectors and particularly to a phase detector being formed by a flip-flop. Phase detectors being formed by a flip-flop are known. However, for the realisation of the known phase detectors several parameters have to be dimensioned individually in order to achieve an optimised phase detector. With the present invention it is no longer necessary to explicitly dimension these parameters. The phase detector has a D-flip-flop (2) with a first output (Q) for generating a control signal (OUT), a first input (C) for a feedback clock, a second input (R) for a pulse (RES) generated from a reference clock (REF), and a third input (D) to which the complemented first output (Q') is coupled and a gate (4,2) for generating the pulse (RES) from the reference clock (REF), whereby an output of the gate (4,2) is coupled back to an input of the gate (4,2). In embodiments, the gate in either formed by an additional D-flip-flop (4) or by an AND-gate (4) and the phase detector D-flip-flop (2). Furthermore additional gates (A1,A2,A3,5) may be provided to minimise the skew of the phase detector. <IMAGE></p> |
