Signal processing device, and driving method and program thereof

摘要

A power switch 307a is provided between a bias generation circuit 301 and a high potential power source, or a power switch 307b is provided between the bias generation circuit 301 and a low potential power source. A bias potential Vb output from the bias generation circuit 301 is held by a potential holding circuit 300. The bias potential Vb held by the potential holding circuit 300 is input to a bias generation circuit 301a, and a bias potential Vb2 output from the bias generation circuit 301a on which an input signal IN is superimposed is input to an amplifier circuit 302. The potential holding circuit 300 is constituted of a capacitor 306 and a switch 305 formed of, for example, a transistor with a low off-state current that is formed using a wide band gap oxide semiconductor. Structures other than the above structure are claimed.

主权项

1. A signal processing device comprising:
a first bias generation circuit including a first transistor, a first resistor, a second resistor and a third resistor; a potential holding portion including a second transistor and a capacitor; an amplifier circuit; and a first wiring to which an input signal is supplied, wherein a first terminal of the second transistor is electrically connected to a first terminal of the capacitor, wherein the first terminal of the capacitor is electrically connected to a gate terminal of the first transistor, wherein a first terminal of the first transistor is electrically connected to a first terminal of the first resistor and a first terminal of the amplifier circuit, wherein the first terminal of the first resistor is electrically connected to the first wiring and a second terminal of the amplifier circuit, wherein a first terminal of the second resistor is electrically connected to the first terminal of the first transistor, wherein a second terminal of the second resistor is electrically connected to the first terminal of the amplifier circuit, wherein a first terminal of the third resistor is electrically connected to the first terminal of the first resistor, and wherein a second terminal of the third resistor is electrically connected to the second terminal of the amplifier circuit.