| 摘要 |
<p>PURPOSE:To stably operate a circuit even at a high frequency by extracting a timing signal from the output signal of an OR circuit, and setting the timing signal as the input signal on the other side of the OR circuit by attaching constant delay time on the timing signal. CONSTITUTION:The OR processing of a stable f0 timing signal having constant delay and an input RZ signal is performed at the OR circuit 22, and the output signal that is a result is inputted to a timing extraction filter 24. Therefore, the stable f0 signal can be obtained at an output terminal 4 even when the continuance of zero occurs in a reception signal. In such a way, a type in which the OR of the timing signal extracted at the input stage of the timing extraction circuit and the input signal is taken is employed. Thereby, it is possible to improve the implementrability of the timing extraction circuit of a fast PCM signal transmission system even by a low Q filter, and to supply a stable clock signal to an identification circuit.</p> |
