| 摘要 |
PROBLEM TO BE SOLVED: To improve memory property by reducing memory cell area or obtaining high-integration in such a way that a layout of interconnect line is optimized. SOLUTION: In a plate line PL of ferroelectric memory cell, plate interconnect lines linearly arranged in a first direction on a memory cell MC of column block CB formed by dividing memory cell array are connected to plate interconnect lines locating beneath the next column block CB by one stage in order with shift portions, and a plate interconnect line of the most lower stage of the column block CB is folded back to a plate interconnect line portion of the most upper stage of the next column block CB. COPYRIGHT: (C)2007,JPO&INPIT
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