Yield optimization of processor with graphene-based transistors

摘要

Techniques described herein generally include methods and systems related to the selection of a combination of graphene and non-graphene transistors in an IC design. To reduce the increase in leakage energy caused by graphene transistors, selected non-graphene transistors may be replaced with graphene transistors in the IC design while other non-graphene transistors may be retained in the IC design. To limit the number of graphene transistors in the IC design, graphene transistors may replace non-graphene transistors primarily at locations in the IC design where significant delay benefit can be realized.

主权项

1. A method to select a combination of heterogeneous transistors in an integrated circuit (IC) design, the method comprising:
identifying, by a computing device, a plurality of levels associated with the IC design, wherein each level includes one or more combinatorial elements that comprise transistors formed with a non-graphene semiconductor material and are configured to receive signals from at least one combinatorial element included in an immediately preceding level of the IC design, at least one sequential element, or a combination of both; selecting, by the computing device, one of the plurality of levels associated with the IC design; replacing, by the computing device, combinatorial elements in the selected one of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a first configuration; determining, by the computing device, an energy leakage rate associated with the first configuration; determining, by the computing device, a time delay associated with the first configuration; comparing, by the computing device, the determined time delay to a target time delay for the IC design and the determined energy leakage rate to a target energy leakage rate for the IC design; and in response to the determined energy leakage rate being less than the target energy leakage rate while the determined time delay meets the target time delay, selecting, by the computing device, another of the plurality of levels associated with the IC design and replacing combinatorial elements in the another of the plurality of levels with combinatorial elements that comprise transistors formed with graphene to form a second configuration, wherein each of the combinatorial elements that comprise transistors formed with graphene has a shorter time delay and a greater energy leakage rate than the respective combinatorial element being replaced.