SYSTEM FOR ERROR CONTROL AND PHASING IN INTERCONNECTED ARQ-CIRCUITS,申请号US19760732995-传众专利搜索

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发明名称	SYSTEM FOR ERROR CONTROL AND PHASING IN INTERCONNECTED ARQ-CIRCUITS
摘要
申请公布号	US4092630(A)	申请公布日期	1978.05.30
申请号	US19760732995	申请日期	1976.10.15
申请人	DE STAAT DER NEDERLANDEN, TE DEZEN VERTEGENWOORDIGD DOOR DE DIRECTEUR-GENERAAL DER POSTERIJEN, TELEGRAFIE EN TELEFONIE	发明人	VAN DUUREN, HENDRIK CORNELIS ANTHONY;DA SILVA, HERMAN
分类号	H04L1/16;G06F11/00;G08C;G08C25/00;H04B1/00;H04L1/18;H04L7/00;(IPC1-7):G08C25/00;H04L1/10	主分类号	H04L1/16
代理机构		代理人
主权项
地址

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