发明名称 DATA RATE CONVERTER
摘要 PURPOSE:To detect a phase difference and to reduce a restoration time from a phase shift even when no frame pulse is received by controlling a post-stage FIFO memory based on the result of comparison between a phase of the output of a pre-stage FIFO memory and that of the post-stage FIFO memory. CONSTITUTION:A reference signal outputted from a reference signal generating circuit 1 is written in FIFO memories 11, 21, 31, 41 of each layer together with 4-layer C-4 data. The phase of the reference signal outputted from the FIFO memories 21, 31, 41 of the 2nd to 4th layers is compared with a phase of the reference signal outputted from the 1st layer FIFO memory 11 by phase comparator circuits 25, 35, 45. When the phases of the both are different, control circuits 26, 36, 46 control the read of the FIFO memories 21, 31, 41 to make the phase of the C-4 frames of each layer in matching with that of the 1st layer. Thus, even when no frame pulse is received, the phases between the layers is always adjusted and the frequency of phase comparison is increased, a restoration time is reduced even if the phases are not in matching with each other.
申请公布号 JPH0856210(A) 申请公布日期 1996.02.27
申请号 JP19930338429 申请日期 1993.12.28
申请人 MATSUSHITA ELECTRIC IND CO LTD;NIPPON TELEGR & TELEPH CORP <NTT> 发明人 SATO KENSUKE;MATSUMOTO KOJIRO;KISHIMOTO RYOZO
分类号 H04J3/04;H04J3/00;H04J3/06;H04L7/00;H04L7/08 主分类号 H04J3/04
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