Epitaxial source/drain differential spacers

摘要

A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.

主权项

1. A method of forming an integrated circuit, comprising the steps of:
forming a first gate on a substrate in an area defined for a first transistor, the first transistor having a first polarity; forming a second gate on the substrate in an area defined for a second transistor, the second transistor having the first polarity; forming a third gate on the substrate in an area defined for a third transistor, the third transistor having a second polarity opposite from the first polarity; forming a conformal epitaxial spacer layer over the substrate; performing a first transistor LDD ion implant process which implants first transistor LDD dopants into the substrate adjacent to the first gate to form first transistor LDD implanted regions of a first conductivity type; performing an epitaxial spacer anisotropic etch process which removes material of the epitaxial spacer layer from horizontal surfaces on the substrate and the first gate so as to leave epitaxial spacers on vertical surfaces adjacent to the first gate, the epitaxial spacers being at least 2 nanometer thick; performing an epitaxial spacer layer etch process which removes substantially all of the epitaxial spacer layer in the area for the second transistor but not in the area for the first transistor; forming an epitaxial blocking layer over the integrated circuit; performing an epitaxial blocking layer etch process which removes material from the epitaxial blocking layer in the area for the first transistor and the area for the second transistor; with the epitaxial spacers on the vertical surfaces adjacent the first gate but not adjacent the second gate, performing a source/drain etch process which removes material from the substrate in source and drain regions of the area for the first transistor and the area for the second transistor, so as to form first source/drain etched regions adjacent to the first gate and second source/drain etched regions adjacent to the second gate; and performing a source/drain epitaxial process which grows source/drain epitaxial material in the first source/drain etched regions and in the second source/drain etched regions to form first epitaxial source/drain regions adjacent to the first gate and second epitaxial source/drain regions adjacent to the second gate, respectively, such that the first epitaxial source/drain regions are separated from the first gate at a top surface of the substrate by a first lateral space on each side of the first gate that is greater by at least 2 nanometers than a second lateral space on each side of the second gate which separates the second epitaxial source/drain regions from the second gate at the top surface of the substrate.