| 摘要 |
PROBLEM TO BE SOLVED: To set the change rate of sampling frequency low without making the frequency of reference clock high. SOLUTION: A reference clock CKg from a reference clock generating circuit is divided by a plurality of dividing circuits FD1 , FD2 ,... to obtain divided clock CKd1 , CKd2 ,.... These divided clock CKd1 , CKd2 ,... are switched by a switching circuit 9 to select one, and this selected clock is outputted as sampling clock CKs to a sequential electrode driving circuit 2. The switching timing of the switching circuit 9 is controlled by a switching control circuit 10 on the basis of a horizontal synchronizing signal Hsync and the reference clock CKg . The dividing circuits FD1 , FD2 ,... output divided clock of unequal intervals if necessary. With the intervals of the divided clock made unequal, the N value of a dividing ratio 1/N can be set to the value other than an integer. Each dividing ratio can therefore be set in proximity so as to suppress the frequency of the reference clock CKg low. |
