发明名称 |
Data processor a method and apparatus for performing postnormalization in a floating-point execution unit |
摘要 |
A method and apparatus for performing prenormalization during execution by an execution unit (100) of a floating-point add/subtract operation using two data operands. The execution unit (100) adds a mantissa portion of a first and a second floating-point data operand to generate a prenormalized mantissa sum. The execution unit (100) minimizes critical path delays to allow high-performance floating-point calculations while simultaneously reducing logic. Instead of treating the prenormalized mantissa sum as a 64-bit value with special treatment in case of a carry out due to overflow, the floating-point adder 100 treats the prenormalized mantissa sum as a 65-bit value, with the most significant bit being a carry output. Instead of conditionally incrementing an initial exponent value, the initial exponent value is always incremented. Thus, allowing the floating-point adder unit 100 to perform the exponent adjustments for normalization and for rounding faster.
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申请公布号 |
US5373461(A) |
申请公布日期 |
1994.12.13 |
申请号 |
US19930000339 |
申请日期 |
1993.01.04 |
申请人 |
MOTOROLA, INC. |
发明人 |
BEARDEN, DAVID R.;VARGAS, RAYMOND L. |
分类号 |
G06F7/00;G06F7/485;G06F7/50;G06F7/76;(IPC1-7):G06F7/38 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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