| 摘要 |
PROBLEM TO BE SOLVED: To reduce a burden of a user in expanding an address bus. SOLUTION: In respective AND operation circuits 1B16 to 1B19 , latch address signals outputted from latch address signal output terminals LA16 to LA19 are inputted and address signals that respectively correspond to the respective latch address signals are inputted among address signals outputted from the address signal output terminals A16 to A19. Output signals of the respective AND operation circuits 1B16 to 1B19 are inputted as an address signal of each high-order bit to an expansion I/F 3. Then, even though an address outputted from a main electronic equipment unit 1 is a real address and even though a high-order 4-bit address is an address of a fixed latch address, an expansion unit 2 can output an address signal corresponding to an address outputted by the main electronic equipment unit 1.
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