| 摘要 |
PROBLEM TO BE SOLVED: To provide a simulation device capable of shortening a verification time on a software level for a verification objective circuit described by an HDL. SOLUTION: This device, which performs simulation by using description information by the HDL and the like representing a predetermined circuit, constructs description information 31 by integrating information 311 showing the verification objective circuit and information 312 showing a test vector circuit, which is connected to the verification objective circuit shown by the information 311 to input/output verification information automatically generated in its own circuit from/to the verification objective circuit, together. COPYRIGHT: (C)2007,JPO&INPIT
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