发明名称 |
SEMICONDUCTOR LOGICAL CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To secure reliability and to prevent the deterioration in operating speed in lower power supply voltage by providing a control circuit supplying a voltage lower than power supply voltage on the high potential side for the gate of an N-channel MOS transistor for dividing voltage when an output signal is at a high level and supplying a voltage higher than the power supply voltage on the high potential side as a control signal when the output signal is at a low level. SOLUTION: A pull-up side MOS transistor Tr1 , a channel MOS transistor for dividing voltage Tr3 and a pull-down side MOS transistor Tr2 are serially connected between the power supply voltage on the high potential side Vcc and a power supply voltage on the low potential side Vss , and a control circuit 1 is connected. Then the control circuit 1 supplies a voltage lower than the level of the power supply voltage on the high potential side Vcc turning on the channel MOS transistor for dividing voltage Tr3 as a control signalϕ1 when the output signal OUT is at a high level and supplies a voltage higher than the power supply voltage on the high potential side Vcc as the control signalϕ1 when the output signal OUT is at a low level.
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申请公布号 |
JPH09261037(A) |
申请公布日期 |
1997.10.03 |
申请号 |
JP19960061318 |
申请日期 |
1996.03.18 |
申请人 |
FUJITSU LTD;FUJITSU VLSI LTD |
发明人 |
NOMURA HIDENORI;NISHIKAWA MASATAKA;SOFUE KOUYA;TOMITA MITSUAKI;ABE NOBUYUKI;KURATA TAKAYOSHI |
分类号 |
H01L21/8238;H01L27/092;H03K19/003;H03K19/0948;H03K19/20;(IPC1-7):H03K19/094;H01L21/823 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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