发明名称 |
BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME |
摘要 |
An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit comprises a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a plurality of sequential input/output bit-pair signals corresponding to an internal data strobe input signal and a phase shifted data strobe output signal respectively. A second multiplexer selects a reference data input bit that corresponds to one of the internal data strobe input signals of the input/output bit pair signals s from the delay line blocks and a third multiplexer for selecting a reference data output bit that corresponds to one of the phase shifted data strobe output signals from the input/output bit pair signals. A phase detector for determining a phase difference between the reference data input bit and the reference data output bit and outputting a phase difference value.
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申请公布号 |
US2009013228(A1) |
申请公布日期 |
2009.01.08 |
申请号 |
US20070772262 |
申请日期 |
2007.07.02 |
申请人 |
JARBOE JR JAMES MICHAEL;PANIGRAHI SUKANTA KISHORE;AGRAWAL VINAY;NAYAK NEERAJ P |
发明人 |
JARBOE, JR. JAMES MICHAEL;PANIGRAHI SUKANTA KISHORE;AGRAWAL VINAY;NAYAK NEERAJ P. |
分类号 |
G06F11/27;G01R31/3187 |
主分类号 |
G06F11/27 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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