Clock generation system with dynamic distribution bypass mode

摘要

In some embodiments, a tight loop mode is provided is which most, if not all of, the clock distribution circuitry may be bypassed during an initial frequency lock stage.

主权项

1. An apparatus, comprising:
a PLL (phase locked loop) circuit to generate a PLL clock at a PLL clock output, the PLL circuit having a feedback path input coupled to an input of a divider; a clock distribution circuit switchably coupled to the PLL clock output to generate a post clock off of the PLL clock; and a switch circuit capable of dynamically switching between the PLL clock and the post clock to be coupled to the feedback path input while the PLL circuit is generating a clock output.