发明名称 CELL RECEPTION PROCESSOR
摘要 <p>PURPOSE: To reduce the circuit scale of an ATM communication system and to shorten the time for processing by receiving and processing a cell while performing communication between a cell receiving part and a CPU through a flag address register. CONSTITUTION: When a cell receiving part 2 receives one cell while no data exist in a memory 3, an end address EN of a flag address register 5 is updated for one cell and a reception flag F is turned to '1'. When a CPU 4 detects flag F being 1, the data in the memory 3 are directly read out while referring to a start address ST and the end address EN. When those data are completely read out, the flag F is turned to '0'. When the CPU 4 detects that the flag F is turned to '0', the cell receiving part 2 updates the start address ST of the flag address register 5 to an address next to the end address EN. When no data exist in the memory, the operation is restarted from the reception of one cell but when any data exist, the operation is restarted from the processing for updating the end address EN by one cell.</p>
申请公布号 JPH08107420(A) 申请公布日期 1996.04.23
申请号 JP19940243704 申请日期 1994.10.07
申请人 FUJITSU LTD 发明人 SATO YOSHIKO;KOBAYASHI KATSUMI;SATO HIROTERU;OBA YASUHIRO
分类号 H04J3/14;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04J3/14
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