| 摘要 |
PURPOSE:To eliminate a line memory and to extremely simplify the constitution of a circuit by inputting image information directly to a memory controlled by a CPU bus. CONSTITUTION:During the output of invalid data from a reading element 41, a CPU 40 executes a dummy instruction to adjust a period. After the execution of the instruction, the CPU 40 inputs effective image information outputted from the element 41 regularly and directly to the memory 43 controlled by the CPU BUS. At that time, the CPU 40 executes the succeeding dummy instruction to make the processing time, i.e., an input period Tb, coincide with the time required for shifting the image information in a shift register 50 by the bit width of a data bus 44. Consequently, the transfer timing of the image information outputted from a reading element control port 54 and the element 41 is synchronized with the input timing of the CPU 40 and the image information is directly inputted and stored to/in the memory 43 based on the synchronized timing.
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