发明名称 |
Testing synchronous bus system - feeding parallel cyclically phase-shifted pseudo-random data stream to inputs of bus system, reversing data stream at output of bus system, and comparing data stream with original quasi-random sequence |
摘要 |
<p>The data of a quasi-random data stream is processed into n parallel identical data streams. The n parallel data streams are cyclically shifted in time relative to each other and are fed to the n inputs of the bus system (2) to be tested. The data streams at the outputs of the bus system (2) are further serialised (3). The previously-carried-out cyclic time shift is then carried out in reverse. By comparing (5) the original quasi-random stream with the serialised data stream taken from the bus output data streams, an error or fault can be determined. The data and time information of a quasi-random stream are fed to a first n stage shift register (1). The data at the outputs of the bus system (2) may then be fed to the parallel inputs of a second shift register (3).</p> |
申请公布号 |
DE19529752(A1) |
申请公布日期 |
1997.02.13 |
申请号 |
DE1995129752 |
申请日期 |
1995.08.12 |
申请人 |
ROBERT BOSCH GMBH, 70469 STUTTGART, DE |
发明人 |
WAHL, KARL-HEINZ, DIPL.-ING., 01900 GROSROEHRSDORF, DE |
分类号 |
G06F11/267;H04L1/24;H04L12/26;(IPC1-7):H04L1/24;G06F11/277 |
主分类号 |
G06F11/267 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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