Providing code sections for matrix of arithmetic logic units in a processor

摘要

The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyzer unit located between the trace cache and the ALUs, wherein the analyzer unit analyzes the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.

主权项

1. A processor comprising:
a trace cache; a plurality of ALUs arranged in a matrix; and an analyser unit connected to the trace cache, the analyser unit:
analysing the code in the trace cache;detecting loops in the code;transforming the code, including arranging the code into sections of the code mapping to multiple ALUs of the plurality of ALUs; andissuing to the multiple ALUs the sections of the code for joint execution of instructions in the sections of code for a plurality of clock cycles, each instruction in one of the sections of code being issued to a different ALU within the matrix, and at least one of the instructions issued to one of the ALUs staying temporarily fixed for a plurality of clock cycles while multiple data words are streamed through the ALU.