| 摘要 |
PURPOSE:To improve a device of this design in latch-up resistance property by a method wherein a source and a drain electrode of a MOS transistor are connected with a first node to which a first power supply potential is applied and a drain electrode of a MOS transistor is connected with a second node to which a second power supply potential is applied. CONSTITUTION:A first node 11 and a second node 12 supplied with a first and a second power supply potential respectively are provided. And, a MOS transistor 26 is provided, where a source electrode 22 and a drain electrode 23 are connected with the said first node 11 and the drain electrode 23 is connected with the said second node 12. When voltage between the gate electrode 24, connected with the first node, of the MOS transistor 26 and the drain electrode 23 connected with the second node exceeds the threshold voltage of this transistor, the resistor is rendered to be on and then the current path is established between the first and the second node, and a surge applied onto one node is absorbed by the other node. By these processes, a latch-up resistant property can be improved.
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