发明名称 Through Silicon Via Structure and Method
摘要 A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.
申请公布号 US2016181157(A1) 申请公布日期 2016.06.23
申请号 US201615054481 申请日期 2016.02.26
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Yu Chen-Hua;Jeng Shin-Puu;Chiou Wen-Chih;Tsai Fang Wen;Tsai Chen-Yu
分类号 H01L21/768;H01L25/065;H01L21/02;H01L25/00 主分类号 H01L21/768
代理机构 代理人
主权项 1. A method comprising: forming a through substrate via in a substrate, the substrate comprising a device substrate and metallization layers over a first side of the device substrate, the through substrate via comprising a first conductive material having a sidewall, a protruding end of the through substrate via protruding from a second side of the device substrate, wherein a liner covers the sidewall of the first conductive material from a first end of the first conductive material to a second end of the first conductive material; forming a first passivation layer over the second side of the device substrate and over the liner, the first passivation layer having a surface that is closer to the device substrate than a protruding end of the through substrate via; recessing the first passivation layer and the liner to expose the sidewall of the first conductive material, wherein the first passivation layer forms a stair-step pattern; and forming a second conductive material in contact with the sidewall of the first conductive material.
地址 Hsin-Chu TW