发明名称 |
Enhancement mode III-nitride device and method for manufacturing thereof |
摘要 |
Enhancement mode III-nitride HEMT and method for manufacturing an enhancement mode III-nitride HEMT are disclosed. In one aspect, the method includes providing a substrate having a stack of layers on the substrate, each layer including a III-nitride material, and a passivation layer having high temperature silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by MOCVD or LPCVD or any equivalent technique at a temperature higher than about 450° C. The method also includes forming a recessed gate region by removing the passivation layer only in the gate region, thereby exposing the underlying upper layer. The method also includes forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region, and forming a gate contact and source/drain contacts. |
申请公布号 |
US9425281(B2) |
申请公布日期 |
2016.08.23 |
申请号 |
US201514701313 |
申请日期 |
2015.04.30 |
申请人 |
IMEC |
发明人 |
Decoutere Stefaan |
分类号 |
H01L29/66;H01L29/205;H01L23/29;H01L21/56;H01L21/02;H01L29/778;H01L29/20 |
主分类号 |
H01L29/66 |
代理机构 |
Knobbe, Martens, Olson & Bear LLP |
代理人 |
Knobbe, Martens, Olson & Bear LLP |
主权项 |
1. A method of manufacturing an enhancement mode III-nitride high electron mobility transistor (HEMT), the method comprising:
providing a substrate comprising a stack of III-nitride layers on the substrate, each layer comprising a III-nitride material, and a passivation layer comprising high temperature (HT) silicon nitride overlying and in contact with an upper layer of the stack of III-nitride layers, wherein the HT silicon nitride is formed by metal-organic chemical vapor deposition (MOCVD) or low pressure chemical vapor deposition (LPCVD) at a temperature higher than about 450° C., wherein the passivation layer is formed in-situ with the stack of III-nitride layers; forming a recessed gate region by removing substantially completely the passivation layer only from a gate region, thereby exposing the underlying upper layer, forming a p-doped GaN layer at least in the recessed gate region, thereby filling at least partially the recessed gate region; and forming a gate contact in the gate region and source/drain contacts through the passivation layer. |
地址 |
Leuven BE |