TRANSMITTER

摘要

PURPOSE:To shorten initial starting time and to remove non-convergence by providing a phase detection part and a clock control part, detecting a state even when the phase of a received signal shows pseudo convergence, executing forced phase control and escaping from a pseudo stable point. CONSTITUTION:Based on an output (a) of an equalizer 2 and an output X of an identifier 3, a phase detection circuit 5 finds the difference between the phase of a current sample clock and the optimum sample phase of a received waveform. According to the output UP/DOWN of the above-mentioned phase detection circuit 5, a clock control circuit 7 changes the frequency dividing ratio of a system clock CK1 and controls the phases of the system clock CK1 and a sample clock CKS1. When the phase detector 5 shows the pseudo convergence because the convergence of the equalizer 2 is not sufficient, such a state is detected and the sample phase of the received signal is forcedly changed and pulled out from the pseudo stable point. Thus, the initial starting time can be shortened and a problem such as starting fault caused by non- convergence can be canceled.